Methods of Forming a Capacitor Structure

ABSTRACT

The invention includes a method of forming a capacitor electrode. A sacrificial material sidewall is provided to extend at least partially around an opening. A first silicon-containing material is formed within the opening to partially fill the opening, and is doped with conductivity-enhancing dopant. A second silicon-containing material is formed within the partially filled opening, and is provided to be less heavily doped with conductivity-enhancing dopant than is the first silicon-containing material. At least some of the second silicon-containing material is converted into hemispherical grain silicon, and at least some of the sacrificial material sidewall is removed. The invention also encompasses methods of forming capacitors and capacitor assemblies incorporating the above-described capacitor electrode. Further, the invention encompasses capacitor assemblies and capacitor structures.

TECHNICAL FIELD

[0001] The invention pertains to methods of forming semiconductorstructures, and in particular embodiments pertains to methods of formingcapacitor electrodes and capacitor assemblies. The invention alsoencompasses capacitor structures, and capacitor-containing assemblies.

BACKGROUND OF THE INVENTION

[0002] Capacitors are utilized in numerous semiconductor structures. Forinstance, capacitors can be coupled with transistors to form dynamicrandom access memory (DRAM) cells. A continuing goal in semiconductordevice fabrication is to shrink the spacing between adjacent devices,and therefore enable an increasing number of devices to be formed withinthe same amount of semiconductor wafer real estate. A problem that canoccur when spacing between adjacent capacitor structures is reduced isthat various conductive components of the adjacent structures can extendacross a gap between the structures, and ultimately cause an electricalshort from one structure to an adjacent structure. Such electrical shortcan alter electrical characteristics associated with the capacitorstructures, and even render the structures inoperable.

[0003] It would be desirable to develop new capacitor structuresdesigned for relatively tight packing between adjacent structures; andit would be further desirable to develop methodologies for forming suchstructures.

SUMMARY OF THE INVENTION

[0004] In one aspect, the invention encompasses a method of forming acapacitor electrode. A sacrificial material sidewall is provided toextend at least partially around an opening. A first silicon-containingmaterial is formed within the opening to partially fill the opening, andis doped with conductivity-enhancing dopant. A second silicon-containingmaterial is formed within the partially filled opening, and is providedto be less heavily doped with conductivity-enhancing dopant than is thefirst silicon-containing material. At least some of the secondsilicon-containing material is converted into hemispherical grainsilicon, and at least some of the sacrificial material sidewall isremoved. The invention also encompasses methods of forming capacitorsand capacitor assemblies incorporating the above-described capacitorelectrode. Further, the invention encompasses capacitor assemblies andcapacitor structures.

[0005] An exemplary capacitor structure encompassed by the inventioncomprises a container construction which includes a firstsilicon-containing layer around a second silicon-containing layer. Thesecond silicon-containing layer defines an inner periphery of thecontainer and the first silicon-containing defines an outer periphery ofthe container. At least some of the second silicon-containing layer isin the form of hemispherical grain silicon. A dielectric material isalong the inner and outer peripheries of the container construction, anda conductive material is over the dielectric material. The containerconstruction, dielectric material and conductive material togetherdefine at least part of the capacitor structure.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

[0007]FIG. 1 is a diagrammatic, cross-sectional view of a semiconductorwafer fragment shown at a preliminary processing step of a method of thepresent invention.

[0008]FIG. 2 is a view of the FIG. 1 wafer fragment shown at aprocessing step subsequent to that of FIG. 1.

[0009]FIG. 3 is a view of the FIG. 1 wafer fragment shown at aprocessing step subsequent to that of FIG. 2.

[0010]FIG. 4 is a view of the FIG. 1 wafer fragment shown at aprocessing step subsequent to that of FIG. 3.

[0011]FIG. 5 is a view of the FIG. 1 wafer fragment shown at aprocessing step subsequent to that of FIG. 4.

[0012]FIG. 6 is a view of the FIG. 1 wafer fragment shown at aprocessing step subsequent to that of FIG. 5.

[0013]FIG. 7 is a view of the FIG. 1 wafer fragment shown at aprocessing step subsequent to that of FIG. 6.

[0014]FIG. 8 is a view of the FIG. 1 wafer fragment shown at aprocessing step subsequent to that of FIG. 7.

[0015]FIG. 9 is a diagrammatic, cross-sectional view of a semiconductorwafer fragment shown at a processing step in accordance with a secondembodiment method of the present invention. The processing step of FIG.9 follows the processing step of FIG. 3.

[0016]FIG. 10 is a view of the FIG. 9 wafer fragment shown at aprocessing step subsequent to that of FIG. 9.

[0017]FIG. 11 is a view of the FIG. 9 wafer fragment shown at aprocessing step subsequent to that of FIG. 10.

[0018]FIG. 12 is a view of the FIG. 9 wafer fragment shown at aprocessing step subsequent to that of FIG. 11.

[0019]FIG. 13 is a view of the FIG. 9 wafer fragment shown at aprocessing step subsequent to that of FIG. 12.

[0020]FIG. 14 is a diagrammatic, cross-sectional view of semiconductorwafer fragment processed in accordance with a third embodiment method ofthe present invention. The processing step of FIG. 14 follows the stepillustrated in FIG. 10.

[0021]FIG. 15 is a view of the FIG. 14 wafer fragment shown at aprocessing step subsequent to that of FIG. 14.

[0022]FIG. 16 is a view of the FIG. 14 wafer fragment shown at aprocessing step subsequent to that of FIG. 15.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] This disclosure of the invention is submitted in furtherance ofthe constitutional purposes of the U.S. Patent Laws “to promote theprogress of science and useful arts” (Article 1, Section 8).

[0024] A first embodiment method of the present invention is describedwith reference to FIGS. 1-8. Referring initially to FIG. 1, asemiconductor wafer fragment 10 comprises a substrate 12 having aninsulative mass 14 thereover. Mass 14 has an upper surface 15.

[0025] Substrate 12 can comprise, for example, monocrystalline silicon,and insulative mass 14 can comprise, for example, borophosphosilicateglass (BPSG).

[0026] To aid in interpretation of the claims that follow, the terms“semiconductive substrate” and “semiconductor substrate” are defined tomean any construction comprising semiconductive material, including, butnot limited to, bulk semiconductive materials such as a semiconductivewafer (either alone or in assemblies comprising other materialsthereon), and semiconductive material layers (either alone or inassemblies comprising other materials). The term “substrate” refers toany supporting structure, including, but not limited to, thesemiconductive substrates described above. Even though material 12 isreferred to above as a “substrate” it is to be understood that the term“substrate” can also be utilized in the context of this disclosure torefer to mass 14, or to refer to the assembly comprising a combinationof masses 12 and 14. For purposes of describing FIGS. 1-8, mass 12 willbe referred to as a “substrate.” However, it is to be understood thatthe term “substrate” utilized in the claims that follow can encompassother materials in combination with, or alternatively to, mass 12.

[0027] A pair of electrical nodes 16 and 18 are supported by substrate12. In the shown construction, an insulative mass 20 is provided betweensubstrate 12 and mass 14; and electrical nodes 16 and 18 are conductiveplugs extending through insulative mass 20. Insulative mass 20 couldcomprise, for example, BPSG, silicon dioxide, or silicon nitride. Plugs16 and 18 can comprise, for example, metals (such as tungsten ortitanium); metal nitrides (such as, for example, tungsten nitride ortitanium nitride); metal silicides (such as, for example, tungstensilicide or titanium silicide) and/or conductively-doped silicon (suchas, for example, conductively-doped polycrystalline silicon).

[0028] Plugs 16 and 18 are shown formed over conductively-dopeddiffusion regions 22 and 24 which extend into substrate 12. Diffusionregions 22 and 24 can comprise either n-type dopant or p-type dopant.Diffusion regions 22 and 24 can correspond to source/drain regionsassociated with transistor devices (not shown). In alternativeembodiments of the invention, conductive plugs 16 and 18 can be omitted,together with mass 20; and mass 14 can be formed directly over substrate12 and diffusion regions 22 and 24. In yet other alternativeembodiments, diffusion regions 22 and 24 can be ommited, and conductiveplugs 16 and 18 can be in electrical connection with other circuitry(not shown) supported by substrate 12.

[0029] Ultimately, the processing of FIGS. 1-8 forms capacitorconstructions in electrical connection with conductive plugs 16 and 18,and plugs 16 and 18 accordingly provide electrical interconnectionbetween the capacitor constructions and other circuitry (not shown)associated with substrate 12. If plugs 16 and 18 are omitted, thecapacitor constructions can be formed in electrical contact withdiffusion regions 22 and 24 without the intervening plugs 16 and 18.

[0030] Referring to FIG. 2, openings 26 and 28 are formed throughinsulative mass 14 and to electrical nodes 16 and 18, respectively. Theopenings have sidewall peripheries 27 and 29, respectively; and bottomperipheries 31 and 33, respectively.

[0031] A conductive material layer 30 is formed across upper surface 15of insulative material 14, and is formed within openings 26 and 28 topartially fill the openings. Layer 30 can be referred to as a firstlayer formed within the openings. In the processing that follows, asubstantial amount of material 30 will ultimately be removed.Accordingly, material 30 can also be referred to as a sacrificialmaterial. Material 30 preferably comprises a metal and/or a metalnitride; and in particular embodiments can comprise one or morematerials selected from the group consisting of elemental titanium,elemental tungsten, titanium nitride, and tungsten nitride. In otherparticular embodiments, material 30 can consist of, or consistessentially of, one or more materials selected from the group consistingof elemental titanium, elemental tungsten, titanium nitride, andtungsten nitride.

[0032] Referring to FIG. 3, wafer fragment 10 is illustrated aftermaterial 30 has been subjected to an anisotropic etch which removesmaterial 30 from over upper surface 15 of mass 14, and further removesmaterial 30 from the majority of the bottom peripheries of openings 26and 28. The remaining portions of material 30 within openings 26 and 28define sidewall spacers 32 and 34 within openings 26 and 28,respectively. In other words, the material 30 remaining within openings26 and 28 extends at least partially around sidewalls of the openings,but does not extend across a majority of the bottom peripheries of theopenings. A suitable anisotropic etch is a plasma dry etch. Inembodiments in which material 30 comprises tungsten, titanium, tungstennitride or titanium nitride; a suitable dry etch can be conducted at aplasma power of from 100 watts to 500 watts, for a time of from 10seconds to 60 seconds, under a pressure of from 10 mTorr to 2 Torr, at atemperature of from 30° C. to 100° C., with an etchant comprisingCl₂-based chemistry Preferably, metal layer 30 will have a thickness offrom about 50 Å to about 200 Å, which can enable a sufficient thicknessof material 30 to provide desired support properties, while also beingsufficiently thin to enable the plasma etch to be conducted in areasonable period of time.

[0033] A first silicon-containing layer 36 is provided over insulativemass 14 and within openings 26 and 28 to partially fill, and accordinglynarrow the openings; and a second silicon-containing layer 38 isprovided over layer 36 and within the narrowed openings. Firstsilicon-containing layer 36 and second silicon-containing layer 38 canbe referred to herein as a second layer and a third layer, respectively,to indicate that the layers follow provision of sacrificial layer 30.

[0034] Silicon-containing layers 36 and 38 can comprise one or both ofamorphous silicon and polycrystalline silicon. Layer 36 is doped withconductivity-enhancing dopant, and is substantially more doped withconductivity-enhancing dopant than is silicon-containing layer 38. Theconductivity-enhancing dopant within layer 36 can be n-type. Preferably,the conductivity-enhancing dopant concentration within layer 36 will beat least 10²⁰ atoms/cm³. Also, the dopant concentration withinsilicon-containing layer 36 will preferably be at least 10³ fold higherthan any dopant concentration in second silicon-containing layer 38,more preferably at least 10⁵ fold higher than any dopant concentrationin silicon-containing layer 38; and even more preferably at least 10¹⁰fold higher than any dopant concentration in silicon-containing layer38. In particular embodiments, first silicon-containing layer 36 can bedoped to a concentration of greater than or equal to 10²⁰ atoms/cm³ withconductivity-enhancing dopant, and second silicon-containing layer 38 issubstantially undoped with conductivity-enhancing dopant silicon. Theterm “substantially undoped” is defined herein to refer to a dopantconcentration of less than 10¹⁵ atoms/cm³.

[0035] Referring to FIG. 4, fragment 10 is illustrated after secondsilicon-containing layer 38 has been exposed to conditions which roughenan outer surface of the layer to form a rugged surface 40. Ruggedsurface 40 can be considered to comprise hemispherical grain silicon.Suitable conditions for forming roughened surface 40 are to expose layer38 to silane gas at a temperature of at least about 550° C. for a timeof less than or equal to about two minutes under a vacuum of less thanor equal to 1×10⁻⁴ Torr to seed the layer, and subsequently annealingthe seeded layer at a temperature of at least about 550° C. for a timeof less than or equal to about 3 minutes.

[0036] Referring to FIG. 5, wafer fragment 10 is illustrated afterremoval of silicon-containing layers 36 and 38 from over mass 14. Suchremoval can be accomplished by planarization, such as, for example,chemical-mechanical polishing. In the shown embodiment, planarizationhas left a substantially flat (i.e., planar) upper surface 42 extendingacross mass 14, sidewall spacers 32 and 34, and the layers 36 and 38.Upper surface 42 can be at the same elevation as the initial uppersurface 15 (FIGS. 1-4) of mass 14, or can be elevationally lower thansuch initial upper surface if some of mass 14 is removed during theplanarization process.

[0037] Referring to FIG. 6, insulative mass 14 is selectively etchedback relative to metal-comprising layer 30 and silicon-containing layers36 and 38. In embodiments in which silicon-containing layers 36 and 38comprise amorphous or polycrystalline silicon, metal-containing layer 30comprises elemental metal or metal nitride, and insulative mass 14comprises BPSG, a suitable etching process for selectively etching theBPSG of mass 14 is diluted HF at 100:1 or 10:1.

[0038] The etch removes some of mass 14 and effectively forms a newupper surface 44 of the mass which is lowered relative to planarizedupper surface 42. Also, the removal of a portion of mass 14 exposesouter edges of sidewalls 32 and 34, with such outer edges being labeledas 45 and 47, respectively. In the shown preferred embodiment, only someof mass 14 is removed, and accordingly only portions of the outer edgesof spacers 32 and 34 are exposed. However, the invention encompassesother embodiments (not shown) wherein an entirety of mass 14 is removed,and accordingly wherein an entirety of the outer edges of spacers 32 and34 are exposed.

[0039] Referring to FIG. 7, exposed portions of spacers 32 and 34 areselectively removed relative to silicon-containing layers 36 and 38; andrelative to insulative mass 44. In embodiments in which sacrificialmaterial 30 comprises elemental titanium, elemental tungsten, titaniumnitride, and/or tungsten nitride; sacrificial mass 44 comprises BPSG;and layers 36 and 38 comprise amorphous and/or polycrystalline silicon;a suitable etch for selectively removing sacrificial material 30 is apirahna etch. The etch can be extensive enough to create a small trench(not shown), or can leave a surface of material 30 approximately levelwith the surface of material 14 as shown.

[0040] The removal of exposed portions of sacrificial material 30 leavescontainer-shaped structures 50 and 52 remaining over conductive plugs 16and 18, respectively. The container-shaped structures comprise an outersilicon-containing layer 36 around an inner silicon-containing layer 38.The inner layer 38 defines inner peripheries 54 and 56 of the containerstructures, and outer silicon-containing layer 36 defines outerperipheries 58 and 60 of the structures. Inner periphery 54 is roughenedrelative to outer periphery 58, and in the shown embodiment outerperiphery 58 is substantially smooth (i.e., the outer periphery has notbeen subjected to conditions which form a rugged silicon surface fromthe silicon of layer 36). Although the shown embodiment has an entiretyof the inner periphery 54 shown as rugged or hemispherical grainsilicon; it is to be understood that the invention encompasses otherembodiments (not shown) wherein only some of the inner periphery 54 isin the form of rugged silicon.

[0041] Container structures 50 and 52 ultimately form electrodes(storage nodes) for capacitor structures. The utilization of relativelysmooth outer peripheral surfaces 58 and 60 allows the containerstructures to be formed in close proximity to one another without riskof shorting between the structures; and the rugged inner peripheralsurfaces 54 and 56 allow a surface area of the electrodes to beincreased relative to that which would exist without the rugged innerperipheries.

[0042] Referring to FIG. 8, container structures 50 and 52 are shownincorporated into capacitor constructions 80 and 82, respectively.Specifically, a dielectric material 62 is shown formed along the innerand outer peripheries of the container structures; and a conductivematerial 64 is shown formed over dielectric material 62. Containerconstruction 50, in combination with dielectric material 62 andconductive material 64 defines capacitor construction 80; and capacitorstructure 52 in combination with dielectric material 62 and conductivematerial 64 defines capacitor construction 82. Dielectric material 62can comprise conventional capacitor dielectric materials, such as, forexample, silicon dioxide and/or silicon nitride; and conductive material64 can comprise any of numerous conductive materials, including, forexample, metal and/or conductively doped silicon.

[0043] Capacitor constructions 80 and 82 can be incorporated intovarious semiconductor circuitry applications. In particular embodiments,capacitors 80 and 82 can be an electrical connection with transistorgates (not shown), and accordingly can be incorporated into DRAM cells.

[0044] Although silicon-containing layer 38 was initially provided witha relatively low concentration of conductivity-enhancing dopant comparedto silicon-comprising material 36, it can be desired that the dopantconcentration within the material 38 be increased when the material isincorporated as part of a electrode in a capacitor construction. Suchincrease in dopant concentration can be accomplished by implantingdopant into material 38 prior to incorporation of material 38 into acapacitor construction, and/or by out-diffusion of dopant from heavilydoped material 36 into material 38. Accordingly, in particularembodiments the materials 36 and 38 incorporated into capacitorconstructions 80 and 82 can have about the same concentration ofconductivity-enhancing dopant as one another. Alternatively, in otherparticular embodiments the amount of conductivity-enhancing dopant inmaterial 36 can remain somewhat higher than the concentration inmaterial 38 in the capacitor constructions, provided that material 38 issufficiently electrically conductive to function as a part of acapacitor electrode.

[0045] A second embodiment of the invention is described with referenceto FIGS. 9-13. In referring to FIGS. 9-13, identical numbering will beused as was utilized above in describing FIGS. 1-8, where appropriate.

[0046] Referring initially to FIG. 9, wafer fragment 10 is illustratedat a processing step subsequent to that described above with referenceto FIG. 3. The layers 36 and 38 described with reference to FIG. 3 havebeen removed from over mass 14. A suitable method for removing layers 36and 38 from over mass 14 is planarization, such as, for example,chemical-mechanical polishing. Such planarization forms a substantiallyplanar upper surface 100 extending across mass 14, and layers 30, 36 and38. Upper surface 100 can be at a same elevational level as was aninitial upper surface of mass 14 (with such initial upper surface beingshown as surface 15 in FIG. 3), or can be elevationally lower thansurface 15 if some of mass 14 is removed during the planarizationprocess.

[0047] Referring to FIG. 10, some of mass 14 is selectively removedrelative to layers 30, 36 and 38. Such selective removal can beaccomplished utilizing processing similar to that discussed above withreference to FIG. 6. The removal of some of mass 14 forms a new uppersurface 102 of mass 14 which is lowered relative to planarized uppersurface 100, and exposes some of sacrificial material 30.

[0048] Referring to FIG. 11, the exposed portion of sacrificial material30 is selectively removed relative to mass 14 and silicon-containinglayers 36 and 38. Such selective removal of sacrificial material 30 canbe accomplished with processing similar to that described above withreference to FIG. 7. It is noted that even though an entirety of theexposed portion of sacrificial material 30 is illustrated as beingremoved in the shown preferred embodiment, the invention encompassesother embodiments (not shown) wherein only some of the exposed portionof material 30 is removed.

[0049] Referring to FIG. 12, wafer fragment 10 is illustrated afterexposure to conditions suitable for forming rugged surface 56 acrossexposed portions of silicon-containing material 38. Suitable conditionscan be identical to those described previously with reference to FIG. 4.It is noted that such conditions also form a rugged silicon surface 110across exposed portions of silicon-containing material 36. However,since silicon-containing material 36 comprises a higher concentration ofdopant than does silicon-containing material 38, the rugged surface 110is less rugged than is rugged surface 56. In other words, even thoughboth surface 110 and surface 56 can be considered to comprisehemispherical grain silicon, the average grain size across surface 110is less than the average grain size across surface 56. In particularembodiments, a maximum grain size across surface 110 will also be lessthan a maximum grain size across surface 56.

[0050] Layers 36 and 38 form container structures 112 and 114 over plugs16 and 18, respectively. The container structures have an outerperiphery defined by roughened surface 110 and an inner peripherydefined by roughened surface 56. The outer periphery is smoother thanthe inner periphery, in that the outer periphery has a surface which isless roughened than the inner periphery.

[0051] Referring to FIG. 13, dielectric material 62 and conductivematerial 64 are formed over container constructions 112 and 114 to formcapacitor structures 120 and 122 from the container structures 112 and114, respectively. An advantage of having the outer peripheral surfacesof containers 112 and 114 less roughened than the inner peripheralsurfaces is that such can enable capacitor structures 112 and 114 to beformed closer together than could be accomplished if the outerperipheral surfaces were as rough as the inner peripheral surfaces. Yet,the roughened inner peripheral surfaces enable a large surface area tobe attained, which can improve capacitive properties associated withcapacitors 120 and 122 relative to those which would occur if lessroughened inner surfaces were utilized. Accordingly, capacitorstructures 120 and 122 have the advantage of being suitable for beingformed in close proximity to one another, while retaining advantagesassociated with roughened electrode surfaces.

[0052] Capacitors 120 and 122 can be referred to as dual-sided containercapacitor constructions, in that the capacitive relationship of thecapacitor materials are maintained across both the inner and outerperipheries of the containers.

[0053] An advantage of leaving the remnant of material 30 at a base ofcontainer structures 112 and 114 is that such can eliminate a so-called“sink-hole” problem which can otherwise occur during an etch-back ofmaterial 14. Specifically, if material 14 were etched entirely back to abase of plugs 16 and 18, and if conductive material 30 were then etchedback to a level of plugs 16 and 18, there would occasionally beincongruities introduced at surfaces of plugs 16 and 18. Suchincongruities are frequently referred to as “sink-holes.” However, byleaving a portion of material 30 remaining in the shown preferredembodiment, such sink-holes can be avoided.

[0054] Another embodiment of the invention is described with referenceto FIGS. 14-16. In referring to FIGS. 14-16, similar numbering will beused as was used above in describing FIG. 1-13, as appropriate.

[0055] Referring initially to FIG. 14, semiconductor fragment 10 isillustrated at a processing step subsequent to that of FIG. 10.Specifically, mass 14 has been etched back to form an upper surface 102which is lower than the planarized upper surface 100 of layers 30, 36and 38. After such removal of a portion of mass 14, fragment 10 isexposed to conditions which roughen an exposed surface ofsilicon-containing layer 38. Such conditions can be identical to thosedescribed above with reference to FIG. 7.

[0056] Referring to FIG. 15, exposed portions of material 30 are removedto leave container shapes 140 and 142 comprising silicon-containinglayers 36 and 38. Container constructions 140 and 142 comprise arelatively smooth outer peripheral surface corresponding to an exposedsurface of silicon-containing material 36; and a rugged inner peripheralsurface corresponding to an exposed surface of silicon-containing 38.

[0057] Referring to FIG. 16, dielectric material 62 and conductivematerial 64 are formed across the container shapes 140 and 142 to formcapacitor constructions 144 and 146.

[0058] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described, since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. A method of forming a capacitor electrode, comprising: providing asacrificial material sidewall at least partially around an opening;forming a first silicon-containing material within the opening topartially fill the opening, the first silicon-containing material beingdoped with conductivity-enhancing dopant; depositing a secondsilicon-containing material within the partially-filled opening; thesecond silicon-containing material being less heavily doped withconductivity-enhancing dopant than is the first silicon-containingmaterial; after depositing the second silicon-containing material,increasing a roughness of at least a portion of a surface thereof; andremoving at least some of the sacrificial material sidewall.
 2. Themethod of claim 1 wherein the first silicon-containing materialcomprises a dopant concentration of at least 10²⁰ atoms/cm³.
 3. Themethod of claim 1 wherein the first silicon-containing materialcomprises a dopant concentration that is at least 10³ fold higher thanany dopant concentration in the second silicon-containing material. 4.The method of claim 1 wherein the first silicon-containing materialcomprises a dopant concentration that is at least 10⁵ fold higher thanany dopant concentration in the second silicon-containing material. 5.The method of claim 1 wherein the first silicon-containing materialcomprises a dopant concentration that is at least 10¹⁰ fold higher thanany dopant concentration in the second silicon-containing material. 6.The method of claim 1 wherein the second silicon-containing material issubstantially undoped.
 7. The method of claim 1 wherein the providingthe sacrificial material sidewall at least partially around the openingcomprises: forming an insulative mass over a substrate; forming theopening in the insulative mass; and partially filling the opening withthe sacrificial material.
 8. A method of forming a capacitor electrode,comprising: providing a sacrificial material sidewall at least partiallyaround an opening; forming a first silicon-containing material withinthe opening to partially fill the opening, the first silicon-containingmaterial being doped with conductivity-enhancing dopant; forming asecond silicon-containing material within the partially-filled opening;the second silicon-containing material being less heavily doped withconductivity-enhancing dopant than is the first silicon-containingmaterial; converting at least some of a surface of the secondsilicon-containing material into a rugged silicon surface; and removingat least some of the sacrificial material sidewall.
 9. The method ofclaim 8 wherein the first silicon-containing material comprises a dopantconcentration of at least 10²⁰ atoms/cm³.
 10. The method of claim 8wherein the first silicon-containing material comprises a dopantconcentration that is at least 10³ fold higher than any dopantconcentration in the second silicon-containing material.
 11. The methodof claim 8 wherein the first silicon-containing material comprises adopant concentration that is at least 10⁵ fold higher than any dopantconcentration in the second silicon-containing material.
 12. The methodof claim 8 wherein the first silicon-containing material comprises adopant concentration that is at least 10¹⁰ fold higher than any dopantconcentration in the second silicon-containing material.
 13. The methodof claim 8 wherein the second silicon-containing material issubstantially undoped.
 14. The method of claim 8 wherein the providingthe sacrificial material sidewall at least partially around the openingcomprises: forming an insulative mass over a substrate; forming theopening in the insulative mass; and partially filling the opening withthe sacrificial material.
 15. The method of claim 8 wherein thesacrificial material is a metal-containing material; and wherein theproviding the sacrificial material sidewall at least partially aroundthe opening comprises: forming an insulative mass over a substrate;forming the opening in the insulative mass; forming the sacrificialmaterial within the opening and over an upper surface of the insulativemass; the sacrificial material partially filling the opening and beingalong sidewalls of the opening and along a bottom of the opening; andexposing the sacrificial material to a plasma etch to remove thesacrificial material from over the upper surface of the mass and fromalong the bottom of the opening.
 16. The method of claim 8 wherein theconverting of at least some of the surface of the secondsilicon-containing material into a rugged silicon surface occurs beforethe removing at least some of the sacrificial material.
 17. The methodof claim 8 wherein the converting of at least some of the surface of thesecond silicon-containing material into a rugged silicon surface occursafter the removing of at least some of the sacrificial material; andwherein at least some of a surface of the first silicon-containingmaterial is converted to a rugged silicon surface during the convertingof at least some of the surface of the second silicon-containingmaterial into a rugged silicon surface.
 18. The method of claim 8wherein, the providing the sacrificial material sidewall at leastpartially around the opening comprises forming an insulative mass over asubstrate; forming the opening in the insulative mass; and partiallyfilling the opening with the sacrificial material; the method furthercomprises forming the first and second silicon-containing materials overan upper surface of the insulative mass while forming the first andsecond silicon-containing materials in the opening; the convertingoccurs while the first and second silicon-containing materials are overthe upper surface of the insulative mass; the first and secondsilicon-containing materials are removed from over the upper surface ofthe insulative mass after the converting; at least some of theinsulative mass is removed to expose a region of the sacrificialmaterial sidewall; and the removing of at least some of the sacrificialmaterial sidewall comprises removing the exposed region of thesacrificial material sidewall.
 19. The method of claim 18 wherein theexposed region of the sacrificial material sidewall is only a portion ofthe sacrificial material sidewall.
 20. The method of claim 18 whereinthe exposed region of the sacrificial material sidewall is an entiretyof the sacrificial material sidewall.
 21. The method of claim 8 wherein,the providing the sacrificial material sidewall at least partiallyaround the opening comprises forming an insulative mass over asubstrate; forming the opening in the insulative mass; and partiallyfilling the opening with the sacrificial material; the method furthercomprises forming the first and second silicon-containing materials overan upper surface of the insulative mass while forming the first andsecond silicon-containing materials in the opening; the first and secondsilicon-containing materials are removed from over the upper surface ofthe insulative mass, and at least some of the insulative mass is removedto expose a region of the sacrificial material sidewall; and theremoving of at least some of the sacrificial material sidewall comprisesremoving the exposed region of the sacrificial material sidewall. 22.The method of claim 21 wherein the converting occurs after the removingof the at least some of the sacrificial material sidewall.
 23. Themethod of claim 21 wherein the converting occurs before the removing ofthe at least some of the sacrificial material sidewall.
 24. The methodof claim 21 wherein the exposed region of the sacrificial materialsidewall is only a portion of the sacrificial material sidewall.
 25. Themethod of claim 21 wherein the exposed region of the sacrificialmaterial sidewall is an entirety of the sacrificial material sidewall.26. A method of forming a semiconductor construction, comprising:providing a substrate having an opening extending therein; the openinghaving a periphery defined by at least one sidewall and a bottom; thesubstrate having an upper surface proximate the opening; forming a stackcomprising layers of sacrificial material, first silicon-containingmaterial and second silicon-containing material along the sidewall ofthe opening; the second silicon-containing material having a higherconcentration of conductivity-enhancing dopant than the firstsilicon-containing material; removing some of the substrate to lower theupper surface of the substrate and thereby expose at least a portion ofthe sacrificial material; removing at least some of the exposed portionof the sacrificial material; and converting the first silicon-containingmaterial to hemispherical grain silicon.
 27. The method of claim 26wherein the first and second silicon-containing materials extend acrossthe bottom of the opening, and wherein the sacrificial material does notextend across a majority of the bottom of the opening.
 28. The method ofclaim 26 wherein the converting occurs before the removing of at leastsome of the exposed portion of the sacrificial material.
 29. The methodof claim 26 wherein the converting occurs after the removing of at leastsome of the exposed portion of the sacrificial material.
 30. The methodof claim 26 wherein the converting occurs after the removing at leastsome of the exposed portion of the sacrificial material and wherein theconverting further comprises converting at least some of the secondsilicon-containing material to hemispherical grain silicon during theconversion of the at least some of the first silicon-containing materialto hemispherical grain silicon.
 31. The method of claim 26 wherein theconverting occurs before the removing of some of the substrate.
 32. Themethod of claim 26 wherein the converting occurs after the removing ofsome of the substrate.
 33. The method of claim 26 wherein the convertingoccurs after the removing of some of the substrate and before theremoving at least some of the exposed portion of the sacrificialmaterial.
 34. The method of claim 26 wherein the sacrificial materialcomprises a metal.
 35. The method of claim 26 wherein the sacrificialmaterial comprises elemental titanium.
 36. The method of claim 26wherein the sacrificial material comprises elemental tungsten.
 37. Themethod of claim 26 wherein the sacrificial material comprises a metalnitride.
 38. The method of claim 26 wherein the sacrificial materialcomprises titanium nitride.
 39. The method of claim 26 wherein thesacrificial material comprises tungsten nitride.
 40. The method of claim26 wherein the substrate comprises borophosphosilicate glass, andwherein the opening is formed into the borophosphosilicate glass. 41.The method of claim 26 wherein the second silicon-containing material issubstantially undoped.
 42. A method of forming a capacitor structure,comprising: forming a container construction comprising a firstsilicon-containing layer around a second silicon-containing layer; thefirst silicon-containing layer being more heavily doped withconductivity-enhancing dopant than the second silicon-containing layer;the second silicon-containing layer defining an inner periphery of thecontainer and the first silicon-containing layer defining an outerperiphery of the container; converting at least some of each of thefirst and second silicon-containing layers to hemispherical grainsilicon; the hemispherical grain silicon from the firstsilicon-containing layer having a smaller average grain size than thehemispherical grain silicon from the second silicon-containing layer;forming a dielectric material along the inner and outer peripheries ofthe container construction; and forming a conductive material over thedielectric material; the container construction, dielectric material andconductive material together defining at least part of the capacitorstructure.
 43. The method of claim 42 wherein the converting comprises:(1) exposing the at least some of each of the first and secondsilicon-containing layers to silane gas and a temperature of at leastabout 550° C. for a time of less than or equal to about 2 minutes undera vacuum of less than or equal to about 1×10⁻⁴ Torr to seed the at leastsome of each of the first and second silicon-containing layers; and (2)annealing the seeded layers at a temperature of at least about 550° C.for a time of less than or equal to about 3 minutes.
 44. The method ofclaim 42 wherein the first silicon-containing layer comprises a dopantconcentration of at least 10²⁰ atoms/cm³.
 45. The method of claim 42wherein the first silicon-containing layer comprises a dopantconcentration that is at least 10³ fold higher than any dopantconcentration in the second silicon-containing layer.
 46. The method ofclaim 42 wherein the first silicon-containing layer comprises a dopantconcentration that is at least 10⁵ fold higher than any dopantconcentration in the second silicon-containing layer.
 47. The method ofclaim 42 wherein the first silicon-containing layer comprises a dopantconcentration that is at least 10¹⁰ fold higher than any dopantconcentration in the second silicon-containing layer.
 48. The method ofclaim 42 wherein the second silicon-containing layer is substantiallyundoped.
 49. A method of forming a capacitor structure, comprising:providing a substrate having an electrical node supported thereby;forming an insulative mass over the electrical node; forming an openingextending through the insulative mass to the electrical node; theopening having a periphery which includes at least one sidewall; forminga first layer along the at least one sidewall of the opening; forming asecond layer along first layer; the second layer comprising siliconwhich is doped with a conductivity-enhancing dopant; forming a thirdlayer along the second layer; any concentration ofconductivity-enhancing dopant in the third layer being less than theconcentration of conductivity-enhancing dopant in the second layer;removing some of the insulative mass to expose at least a portion of thefirst layer; removing at least some of the exposed portion of the firstlayer to expose at least some of the second layer; converting at leastsome of the third layer to hemispherical grain silicon; forming adielectric material along the third layer and exposed portion of thesecond layer; and forming a conductive material over the dielectricmaterial; the second layer, third layer, dielectric material andconductive material together defining at least part of the capacitorstructure.
 50. The method of claim 49 wherein the first layer comprisesa metal.
 51. The method of claim 49 wherein the second layer comprises adopant concentration of at least 10²⁰ atoms/cm³.
 52. The method of claim49 wherein the second layer comprises a dopant concentration that is atleast 10³ fold higher than any dopant concentration in the third layer.53. The method of claim 49 wherein the second layer comprises a dopantconcentration that is at least 10⁵ fold higher than any dopantconcentration in the third layer.
 54. The method of claim 49 wherein thesecond layer comprises a dopant concentration that is at least 10¹⁰ foldhigher than any dopant concentration in the third layer.
 55. The methodof claim 49 wherein the converting occurs before the removing at leastsome of the exposed portion of the first layer.
 56. The method of claim49 wherein the converting occurs after the removing at least some of theexposed portion of the first layer.
 57. The method of claim 49 whereinthe converting occurs after the removing at least some of the exposedportion of the first layer and wherein the converting further comprisesconverting at least some of the second layer to hemispherical grainsilicon during the conversion of the at least some of the third layer tohemispherical grain silicon.
 58. The method of claim 49 wherein theconverting occurs before the removing of some of the insulative mass.59. The method of claim 49 wherein the converting occurs after theremoving of some of the insulative mass.
 60. The method of claim 49wherein the converting occurs after the removing of some of theinsulative mass and before the removing at least some of the exposedportion of the first layer.
 61. A capacitor structure comprising: acontainer construction comprising a first silicon-containing layeraround a second silicon-containing layer; the second silicon-containinglayer defining an inner periphery of the container construction and thefirst silicon-containing layer defining an outer periphery of thecontainer construction; the outer periphery of the containerconstruction having a smoother surface than the inner periphery of thecontainer construction; at least some of the second silicon-containinglayer being in the form of hemispherical grain silicon; a dielectricmaterial along the inner and outer peripheries of the containerconstruction; and a conductive material over the dielectric material;the container construction, dielectric material and conductive materialtogether defining at least part of the capacitor structure.
 62. Thecapacitor structure of claim 61 wherein the first silicon-containinglayer is more heavily doped with conductivity-enhancing dopant than thesecond silicon-containing layer.
 63. The capacitor structure of claim 61wherein at least some of the first silicon-containing layer is in theform of hemispherical grain silicon; the hemispherical grain silicon ofthe first silicon-containing layer having a smaller average grain sizethan the hemispherical grain silicon of the second silicon-containinglayer.
 64. A capacitor-containing assembly, comprising: a substratesupporting an electrical node; an insulative mass over the substrate andhaving an opening extending therethrough to the electrical node; theopening having a sidewall periphery and a bottom periphery; theinsulative mass having an upper surface proximate the opening; aconductive material extending along the sidewall periphery of theopening, but not extending along a majority of the bottom periphery ofthe opening: the conductive material not extending above the uppersurface of the insulative mass; a first silicon-containing layer againstthe conductive material and within the opening; the firstsilicon-containing layer defining a container shape extending along thesidewall periphery of the opening and along the bottom periphery of theopening; the first silicon-containing layer extending to above the uppersurface of the insulative mass; an outer surface of the container shapeof the first silicon-containing layer having a first roughness; a secondsilicon-containing layer within the container-shape defined by the firstsilicon-containing layer; the second silicon-containing layer extendingalong the sidewall periphery of the opening and along the bottomperiphery of the opening; the second silicon-containing layer extendingto above the upper surface of the insulative mass; at least some of thesecond silicon-containing layer being in the form of a rugged siliconhaving a surface roughness greater than the first roughness; adielectric material against the second silicon-containing layer andagainst a portion the first silicon-containing layer; and a conductivematerial over the dielectric material; the container first and secondsilicon-containing layers, dielectric material and conductive materialtogether defining at least part of the capacitor structure.
 65. Theassembly of claim 64 wherein the insulative mass comprisesborophosphosilicate glass.
 66. The assembly of claim 64 wherein theconductive material comprises a metal.
 67. The assembly of claim 64wherein the conductive material comprises elemental titanium.
 68. Theassembly of claim 64 wherein the conductive material comprises elementaltungsten.
 69. The assembly of claim 64 wherein the conductive materialcomprises a metal nitride.
 70. The assembly of claim 64 wherein theconductive material comprises titanium nitride.
 71. The assembly ofclaim 64 wherein the conductive material comprises tungsten nitride. 72.The assembly of claim 64 wherein the first silicon-containing layer ismore heavily doped with conductivity-enhancing dopant than the secondsilicon-containing layer.
 73. The assembly of claim 64 wherein at leastsome of the first silicon-containing layer of the outer surface is inthe form of hemispherical grain silicon and wherein the rugged siliconof the second silicon-containing layer is in the form of hemisphericalgrain silicon; the hemispherical grain silicon of the firstsilicon-containing layer having a smaller average grain size than thehemispherical grain silicon of the second silicon-containing layer.